STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications, announced the successful production of the world’s first semiconductor wafer whose ...
A new technical paper titled “Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip” was published by researchers at Inha University and Teradyne. ...
Wafer inspection has become a critical part of the semiconductor manufacturing process. Inspections performed after wafer test can analyze the marks left by probe cards to ensure that the test process ...
Although it requires a new generation of test equipment, testing MEMS devices is challenging but not impossible. Since the early days of the IC industry, wafer-level test has been possible using ...
FREMONT, CA / ACCESSWIRE / December 14, 2023 / Aehr Test Systems (NASDAQ:AEHR), a worldwide supplier of semiconductor test and burn-in equipment, today announced it has received an initial customer ...
Wafer-level burn-in is Aehr's key differentiator: the company says its FOX systems and patented WaferPak enable screening of failing devices before advanced packaging and are offered as a turnkey ...
FREMONT, Calif., Oct. 06, 2022 (GLOBE NEWSWIRE) -- Aehr Test Systems (NASDAQ: AEHR), a worldwide supplier of semiconductor test and reliability qualification equipment, today announced it has released ...
High testing parallelism can be achieved with contactless wafer testing, which leads to reduced production cycle times. It also eliminates the possibility of wafer damage during testing. According to ...
Raman spectroscopy uses inelastic scattering of protons from molecules that are covalently bound in order to identify functional groups, stresses, strains and crystallinity. It is a tool that is ...
Xintec Inc., TSMC's backend packaging and testing unit, posted a strong second-quarter 2025 rebound in wafer probe revenue, driven by increased outsourcing from TSMC and the accelerated ramp of a ...
In a heterogeneous integrated system, the impact of composite yield fallout due to a single chiplet is creating new performance imperatives for wafer test in terms of test complexity and coverage.
As co-packaged optics (CPO) move from concept to deployment, glass-based waveguides are emerging as a key technology for ...
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